1. Technical Field
The present invention relates to analog demultiplexer for distributing signals from a single input line to one of multiple output lines. In particular, the present invention relates to an analog demultiplexer for distributing a video input signal to one of several video display column drivers, with the analog demultiplexer having minimal offset due to its amplifiers, and having a minimal amplifier settling time.
2. Related Art
FIG. 1 shows one conventional configuration for an analog demultiplexer. The analog demultiplexer allows a multiplexed analog input voltage VIN received at input 2 to be demultiplexed using a switch S1 to provide an output voltage VOUT1–VOUTN at a respective one of outputs 41–4N. The logic control driving switch S1 toggles switch S1 to direct an input voltage VIN to one specific output buffer AMP1–AMPN. In this way, an input voltage provided at input VIN can be demultiplexed to one of numerous output buffers AMP1–AMPN.
Assuming the input voltage VIN at input 2 is to be sampled as output voltage VOUT1 at output 41, switch S1 closes to connect amplifier A1 to the capacitor C1 and the input of amplifier AMP1. The voltage at VIN is sampled onto capacitor C1 and the buffered voltage appears on VOUT1. Then the switch S1 is opened. The hold capacitor C1 retains the sampled voltage, and thus, the voltage at VOUT1 remains constant for a period of time. In a similar manner, the input voltage VIN at input 2 can be connected using switch S1 to sample and hold the input voltage VIN using another one of the capacitors C2–CN and its corresponding amplifier AMP2–AMPN.
The undesirable effects of the analog demultiplexer of the configuration of FIG. 1 are as follows:    (1) The amplifiers A1 and AMP1–AMPN all create a voltage offset from the signal at VIN;    (2) The amplifiers A1 and AMP1–AMPN are all shown with a gain of +1, but gain errors occur;    (3) A pedestal voltage offset error occurs when the switch S1 opens; and    (4) The output amplifiers AMP1–AMPN are NOT identical—Or the same input voltage at VIN generates a different output at each output VOUT1–VOUTN.
To improve the performance of analog demultiplexers, several approaches have been used. These approaches are described to follow.
1st Improvement
A first improvement over the analog demultiplexer of FIG. 1 is shown in FIG. 2. In operation, assuming the voltage VIN at input 2 is to be sampled as an output voltage VOUT1 at output 41, then switch S1 closes and connects the output of amplifier A1 to capacitor C1 and the non-inverting input of amplifier AMP1. At the same instant a second switch S2 closes, connecting the output of amplifier AMP1 to the inverting input of amplifier A1. Note components carried over from FIG. 1 to FIG. 2 are similarly labeled, even though they are connected in a different manner, as will be components carried over into subsequent figures. The equivalent circuit for this switch state for FIG. 2 is shown in FIG. 3.
With feedback from output amplifier AMP1 to A1, the equivalent circuit is assumed to have a unity gain configuration. Assuming that the circuit is stable and the gain of both amplifier A1 and amplifier AMP1 are very large, any offset of AMP1 is divided down by the gain of A1. The voltage VIN plus the offset of amplifier A1 is sampled onto the hold capacitor C1. So,VOUT1=VIN+Vos(offset of A1)
Advantages of the configuration of FIG. 2 are as follows:    (1) The voltage offset of AMP1 is divided down by the gain of A1; and    (2) The gain error or AMP1 is divided down by the gain of A1.
Undesirable effects of the configuration of FIG. 2 are as follows:    (1) The voltage offset of amplifier A1;    (2) A voltage offset caused by charge injection of switch S2 when it opens;    (3) The gain error of amplifier A1; and    (4) A long settling time after switch S2 closes.
Before switch S2 of FIG. 2 closes, amplifier A1 would be in an open loop configuration. Thus, its output will be in an undetermined voltage state. Amplifier A1 is “saturated”. Amplifier A1 returns into its “active” region by glitching and ringing its output before it settles. (Settling time depends on the Bandwidth and Phase Margin of the cascaded amplifiers). When the output of amplifier A1 rings, so does VOUT1, an undesirable effect.
2nd Improvement
A second improvement over the analog demultiplexer of FIG. 1 is shown in FIG. 4. In the circuit of FIG. 4, a hold capacitor C1, C2, etc. is placed between the inverting input and output of each of the output amplifiers AMP1, AMP2, etc. Switches S1 and S2 operate as a pair to connect one of the output amplifiers AMP1, AMP2, . . . between the output of amplifier A1 and its non-inverting input. A switch S3 connects the output of A1 to a reference voltage VREF when the switches S1 and S2 are not connected. The non-inverting input of the output amplifiers AMP1, AMP2, . . . are likewise connected to the reference VREF.
In operation it is first assumed that VIN is to be sampled to VOUT1. Switch S1 then closes and connects the output of amplifier A1 to capacitor C1 and the inverting input of amplifier AMP1. At the same instant, switch S2 closes, connecting the output of amplifier AMP1 to the non-inverting input of amplifier A1. Switches S1 and S3 are non-overlapping, or are not connected at the same time. The equivalent circuit of such a connection is shown in FIG. 5.
With feedback, the circuit is in a unity gain configuration. If the gain of amplifier A1 and AMP1 are large, thenVOUT1˜VIN+Vos1 (offset of amplifier A1).
With amplifier AMP1 in a feedback path, its inverting input (which is also the output of amplifier A1) is approximately equal to VREF. For this unity-gain configuration to settle fast, both sides of switch S1 have to be approximately VREF before switch S1 closes.
So, the output of the amplifier A1 should be approximately at VREF before switch S1 closes. This is done by clamping the output of A1 to VREF by turning on switch S3 (note: switch S1 and S3 are non-overlapping). This ensures that amplifier A1 stays in the “active” region resulting in a faster settling time.
Advantages of the configuration of FIG. 4 are as follows:    (1) The voltage offset of AMP1 is divided down by the gain of A1, and is negligible.    (2) The settling time is reduced (Voltage at both sides of switch S1 are approximately the same and amplifier A1 is in its active region when switch S1 closes).    (3) The gain error of AMP1 is divided down by the gain of A1.
Undesirable effects of the configuration of FIG. 4 are as follows:    (1) The voltage offset of amplifier A1 remains;    (2) The gain error of amplifier A1 remains; and    (3) Charge injection of switch S1 to the output capacitor causing an offset error on the output.